Crystalline semiconductor and oxide semiconductor thin-film transistor device and method of manufacturing the same

ABSTRACT

A method of manufacturing a semiconductor device. A pre first semiconductor pattern having a crystalline semiconductor material is formed on a base substrate. A pre first insulation layer is formed on the pre first semiconductor pattern. A first semiconductor pattern is formed by defining a channel region in the pre first semiconductor pattern. A pre protection layer is formed on the pre first insulation layer. A pre second semiconductor pattern including an oxide semiconductor material is formed on the pre protection layer. A pre second insulation layer is formed on the pre second semiconductor pattern. The pre second insulation layer is patterned using an etching gas such that at least a portion of the pre second semiconductor pattern is exposed. A second semiconductor pattern is formed by defining a channel region in the pre second semiconductor pattern. The pre protection layer has a material with a first etch selectivity that is different from a second etch selectivity of the second insulation layer with respect to the etching gas.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119 of Korean PatentApplication No. 10-2016-0111011, filed on Aug. 30, 2016, in the KoreanIntellectual Property Office, the disclosure of which is incorporated byreference herein in its entirety.

TECHNICAL FIELD

Exemplary embodiments of the present inventive concept relate to asemiconductor device and a method of manufacturing the same. Moreparticularly, exemplary embodiments relate to a semiconductor devicewith improved reliability and a method of manufacturing the same.

DISCUSSION OF THE RELATED ART

A semiconductor device includes at least one thin film transistor. Thethin film transistor may include a semiconductor pattern made of asemiconductor material. A display device as an embodiment of asemiconductor device may include a plurality of pixels, and at least onedriving circuit for controlling the plurality of pixels. The drivingcircuit may include at least one thin film transistor. The thin filmtransistors included in the driving circuit may provide electric signalsfor controlling the plurality of pixels.

Each of the pixels may include a pixel driving circuit and a displayelement connected to the pixel driving circuit. The pixel drivingcircuit may include at least one thin film transistor and a capacitor.The thin film transistor and the capacitor constituting the pixeldriving circuit may control the display element according to an electricsignal provided from the pixel driving circuit.

SUMMARY

According to an exemplary embodiment of the present inventive concept, amethod of manufacturing a semiconductor device includes forming a prefirst semiconductor pattern having a crystalline semiconductor materialon a base substrate, and forming a pre first insulation layer on the prefirst semiconductor pattern. The method further includes forming a firstsemiconductor pattern by defining a channel region in the pre firstsemiconductor pattern, and forming a pre protection layer on the firstinsulation layer. The method still further includes forming a pre secondsemiconductor pattern having an oxide semiconductor material on the preprotection layer, and forming a pre second insulation layer on the presecond semiconductor pattern. The method further includes patterning thepre second insulation layer using an etching gas such that at least aportion of the pre second semiconductor pattern is exposed, and forminga second semiconductor pattern by defining a channel region in the presecond semiconductor pattern. The pre protection layer has a materialwith a first etch selectivity that is different from a second etchselectivity of the pre second insulation layer with respect to theetching gas.

According to an exemplary embodiment of the present inventive concept, asemiconductor device includes a base substrate; and a first transistordisposed on the base substrate. The first transistor has a first inputelectrode, a first output electrode, a first control electrode, and afirst semiconductor pattern. The first semiconductor pattern includes acrystalline semiconductor. The semiconductor device further includes asecond transistor disposed on the base substrate. The second transistorhas a second input electrode, a second output electrode, a secondcontrol electrode, and a second semiconductor pattern. The secondsemiconductor pattern includes an oxide semiconductor. The semiconductordevice still further includes a first insulation layer and a secondinsulation layer. The first insulation layer and the second insulationlayer are disposed on the base substrate. The semiconductor devicefurther includes a protection layer disposed between the firstsemiconductor pattern and the second semiconductor pattern and having ametal oxide.

According to an exemplary embodiment of the present inventive concept, asemiconductor device comprises a base substrate, a first semiconductorpattern disposed on the base substrate, the first semiconductor patterncomprising a first channel region and a plurality of first non-channelregions, the first channel region including a crystalline semiconductor,a second semiconductor pattern disposed on the base substrate, thesecond semiconductor pattern comprising a second channel region and aplurality of second non-channel regions, the second channel regionincluding an oxide semiconductor, a first insulation layer disposed onthe base substrate, a protection layer disposed on the first insulationlayer, and an organic light emitting diode comprising a first electrode,a second electrode, and at least one light emitting layer.

The first insulation layer is disposed between first semiconductorpattern and the second semiconductor pattern, and the protection layeris disposed between the first semiconductor pattern and the secondsemiconductor pattern.

The semiconductor device according to an embodiment of the presentinventive concept may further comprise a first control electrodedisposed between the first insulation layer and the protection layer,and a second control electrode disposed on the second semiconductorpattern.

The semiconductor device according to an embodiment of the presentinventive concept may further comprises a first input electrode and afirst output electrode connected to one of the plurality of firstnon-channel regions, respectively, a second input electrode and a secondoutput electrode connected to one of the plurality of second non-channelregions, respectively, the organic light emitting diode connected to atleast one of the first input electrode, the first output electrode, thesecond input electrode, or the second output electrode.

In an embodiment, the protection layer includes a material with a firstetch rate, and the first insulation layer includes a material with asecond etch rate, the second etch rate being different from the firstetch rate for an etching gas.

In an embodiment, the crystalline semiconductor includes apolycrystalline silicon, and the oxide semiconductor includes at leastone of zinc, indium, gallium, tin, or titanium.

The semiconductor device according to an embodiment of the presentinventive concept may further comprises a first capacitor electrodedisposed on the first insulation layer, and a second capacitor electrodepositioned on the protection layer relative to the first capacitorelectrode to form an electric field therebetween.

In an embodiment, the first capacitor electrode and the first controlelectrode are electrically connected to each other.

BRIEF DESCRIPTION OF THE FIGURES

The above and other features of the inventive concept will become moreapparent by describing in detail exemplary embodiments thereof, withreference to the accompanying drawing, which:

FIG. 1 is a block diagram of a semiconductor device according to anexemplary embodiment of the present inventive concept;

FIG. 2 is a cross-sectional view showing a portion of a semiconductordevice according to an exemplary embodiment of the present inventiveconcept;

FIG. 3 is a cross-sectional view showing a portion of a semiconductordevice according to an exemplary embodiment of the present inventiveconcept;

FIG. 4A is a cross-sectional view showing a portion of a semiconductordevice according to an exemplary embodiment of the present inventiveconcept;

FIG. 4B is a cross-sectional view showing a portion of a semiconductordevice according to an exemplary embodiment of the present inventiveconcept;

FIGS. 5A through 5M are cross-sectional views showing a method ofmanufacturing a semiconductor device according to exemplary embodimentsof the present inventive concept; and

FIGS. 6A through 6G are cross-sectional views showing a method ofmanufacturing a semiconductor device according to exemplary embodimentsof the present inventive concept.

DETAILED DESCRIPTION

Exemplary embodiments of the present inventive concept will be describedmore fully with reference to the accompanying drawings. The presentdisclosure may, however, be embodied in many different forms and shouldnot be construed as limited to the embodiments set forth herein. It willbe understood that when an element is referred to as being “connected”to another element, it can be directly connected to the other element orintervening element may be present.

FIG. 1 is a block diagram of a semiconductor device according to anexemplary embodiment of the present inventive concept. The semiconductordevice may include at least one semiconductor pattern. In FIG. 1, adisplay device is shown as an exemplary embodiment of the semiconductordevice. Hereinafter, a display device will be described as an exemplaryembodiment. However, a semiconductor device according to an exemplaryembodiment of the present inventive concept may include variousexemplary embodiments, and is not limited to any one exemplaryembodiment.

As shown in FIG. 1, a display device includes a timing controller TC, ascan driving circuit SDC, a data driving circuit DDC, and a displaypanel DP. The display panel displays an image according to an electricsignal.

The timing controller TC may receive input image signals (now shown),may convert data formats of the input image signals to other dataformats to meet interface specifications with the scan driving circuitSDC, and may generate image data D-RGB. The timing controller TC mayoutput the image data D-RGB and various control signals including adigital control circuit DCS and a scan control signal SCS.

The scan driving circuit SDC may receive the scan control signal SCSfrom the timing controller TC. The scan control signal SCS may include avertical start signal for operating the scan driving circuit SDC, and aclock signal for determining timing outputting signals.

The scan driving circuit SDC may generate a plurality of scan signals,and sequentially outputs the scan signals to a plurality of scan linesSL1 to SLn. Also, the scan driving circuit SDC may generate a pluralityof light emitting control signals in response to the scan control signalSCS, and may output the light emitting control signals to a plurality oflight emitting lines EL1 to ELn.

In FIG. 1, the scan signals and the light emitting control signals areillustrated to be outputted from one scan driving circuit SDC. However,the present inventive concept is not limited thereto. In an exemplaryembodiment of the present inventive concept, scan driving circuits SDCsmay divide and output scan signals, and may divide and output lightemitting control signals. Also, in an exemplary embodiment of thepresent inventive concept, a driving circuit which generates and outputsscan signals, and a driving circuit which generates and outputs lightemitting control signals may be considered to be separate from eachother.

The data driving circuit DDC may receive a data control signal DCS andimage data D-RGB from the timing controller TC. The data driving circuitmay convert the image data D-RGB to data signals, and may output thedata signals to data lines DL1 to DLm. The data signals may be analoguevoltages corresponding to grey scale values of the image data D-RGB.

The display panel DP may include the scan lines SL1 to SLn, the lightemitting lines EL1 to ELn, the data lines DL1 to DLm, and pixels PX. Thescan lines SL1 to SLn may be extended in a first direction DR1, andarranged in a second direction DR2 which crosses the first directionDR1.

Each of the plurality of light emitting lines EU to ELn may be arrangedin parallel to a corresponding scan line among the scan lines SL1 toSLn. The data lines DL1 to DLm may cross the scan lines SL1 to SLn whilebeing insulated therefrom.

Each of the plurality of pixels may be connected to a corresponding scanline among the scan lines SL1 to SLn, to a corresponding light emittingline among the light emitting lines EL1 to ELn, and to a correspondingdata line among the data lines DL1 to DLm.

Each of the pixels PX may receive a first voltage ELVDD corresponding toa power voltage, and a second voltage ELVSS which may be lower in levelthan the first voltage ELVDD. Each of the pixels PX may be connected toa power line PL having the first voltage ELVDD applied thereto. Each ofthe pixels PX may be connected to an initialization line RL receiving aninitialization voltage Vint.

Each of the pixels PX may be electrically connected to three scan lines.As shown in FIG. 1, pixels in the second pixel line may be connected tothe first to third scan lines SL1 to SL3.

Although not shown, the display panel DP may further include a pluralityof dummy scan lines. The display panel DP may still further include adummy scan line connected to pixels PX in the first pixel line, and adummy scan line connected to pixels PX in the n^(th) pixel line. Also,pixels (hereinafter, pixels in pixel lines) connected to one data lineamong the data lines DL1 to DLm may be connected to each other. Twoadjacent pixels among pixels in pixel lines, may be electricallyconnected.

Each of the plurality of pixels PX may include an organic light emittingdiode (now shown), and a pixel driving circuit (not shown) configured tocontrol light emission of the organic light emitting diode. The pixeldriving circuit may include a plurality of thin film transistors, and acapacitor. At least one of the scan driving circuit SDC or the datadriving circuit DDC may include thin film transistors formed thoughsubstantially the same process for a pixel driving circuit.

Through a plurality of a photolithography process, the scan lines SL1 toSLn, the light emitting lines EL1 to ELn, the data lines DL1 to DLm, thepower line PL, the initialization line RL, the pixels PX, the scandriving circuit SDC, and the data driving circuit DDC may be formed on abase substrate (not shown). Through a plurality of a deposition processor a coating process, insulation layers may be formed on the basesubstrate (not shown). Each of the insulation layers may be a thin filmcovering the display panel DP substantially entirely, or may include atleast one insulation pattern overlapping a specific component of thedisplay panel DP. The insulation layers may include an organic layerand/or an inorganic layer. In addition, an encapsulation layer (notshown) protecting the pixels PX may further be provided on the basesubstrate.

FIG. 2 is a cross-sectional view showing a portion of a semiconductordevice according to an exemplary embodiment of the present inventiveconcept. FIG. 2 shows a portion of a pixel among the pixels PXillustrated in FIG. 1. Hereinafter, referring to FIG. 2, a semiconductordevice SD1 will be described.

The semiconductor device SD1 may include a base substrate SUB, a firsttransistor T1, a second transistor T2, a capacitor CST, and an organiclight emitting diode OLED. The upper surface of the base substrate SUBmay be defined by the first direction DR1 (See, for example, FIG. 1) andthe second direction DR2 (See, for example, FIG. 1).

The first transistor T1 may include a first input electrode IE1, a firstoutput electrode OE1, a first control electrode CE1, and a firstsemiconductor pattern SP1. The first transistor T1 may be a drivingtransistor connected to the organic light emitting diode OLED. Thesecond transistor T2 may include a second input electrode IE2, a secondoutput electrode OE2, a second control electrode CE2, and a secondsemiconductor pattern SP2. The second transistor T2 may be a controltransistor to turn on a pixel PX.

The capacitor CST may include a first capacitor electrode CPE1 and asecond capacitor electrode CPE2. The first capacitor electrode CPE1 andthe second capacitor electrode CEP2 may be disposed with an insulationfilm in between while being spaced apart from each other, for example,as shown in FIG. 2.

The organic light emitting diode OLED may include a first electrode ED1,a first charge control layer HCL, a light emitting layer EML, a secondcharge control layer ECL, and a second electrode ED2. In this exemplaryembodiment, the first electrode ED1, the first charge control layer HCL,the light emitting layer EML, the second charge control layer ECL, andthe second electrode ED2 may, respectively, correspond to an anodeelectrode, a hole control layer, a light emitting layer, an electroncontrol layer, and a cathode electrode of an OLED known by a person ofordinary skill in the art. Meanwhile, the OLED may be illustrated by wayof another example. For example, the first electrode ED1, the firstcharge control layer HCL, the light emitting layer EML, the secondcharge control layer ECL, and the second electrode ED2 may,respectively, be a cathode electrode, an electron control layer, a lightemitting layer, a hole control layer, and an anode electrode of an OLEDknown by a person of ordinary skill in the art.

The base substrate SUB may be a layer, a film, or a plate on which thefirst transistor T1, the second transistor T2, and the capacitor CST maybe disposed. The base substrate SUB may include a plastic substrate, aglass substrate, a metal substrate, and the like. The plastic substratemay include at least one of an acrylic resin, a methacrylic resin,polyisoprene, a vinyl-based resin, an epoxy-based resin, aurethane-based resin, a cellulose-based resin, a siloxane-based resin, apolyimide-based resin, a polyamide-based resin, or a perylene-basedresin.

A buffer layer BFL may be disposed between the upper surface of the basesubstrate SUB, and the first transistor T1 and the second transistor T2.The buffer layer BFL may improve bonding force between the basesubstrate SUB and electrically conductive patterns, or semiconductorpatterns. The buffer layer BFL may include one of an inorganic materialand/or an organic material. Although not shown separately, a barrierlayer preventing foreign matters from inflowing may further be disposedon the upper surface of the base substrate SUB. The buffer layer BFL andthe barrier layer may selectively be disposed, or omitted.

On the buffer layer BFL, the first semiconductor pattern SP1 may bedisposed. The first semiconductor pattern SP1 may include a crystallinesemiconductor material. For example, the first semiconductor pattern SP1may include a polycrystalline semiconductor material such aspolycrystalline silicon.

The first semiconductor pattern SP1 may be divided into a first areaAR11 and a third area AR13 with both the first area AR11 and the thirdareas AR13 including impurities, and a second area AR12 which ispositioned right next to the first area AR11 and the third area AR13.The first semiconductor pattern SP1 may be a p-type or an n-typedepending on a type of impurities.

The first area AR11 may be connected to the first input electrode IE1,and the third area AR13 may be connected to the first output electrodeOE1. The second area AR12 may be disposed between the first area AR11and the third area AR13, and may overlap the first control electrode CE1when viewed in a plane in the third direction DR3. The second area AR12may be a channel region of the first transistor T1.

The channel region of the first transistor T1 may include apolycrystalline semiconductor material. Accordingly, the firsttransistor T1 may have an improved mobility, and may serve as a drivingelement having high reliability. In the channel region of the firstsemiconductor pattern SP1, a hole may move, or an electron may movedepending on a structure of the first semiconductor pattern SP1. Forexample, in the channel region AR12 of the first semiconductor patternSP1, a hole or an electron may move depending on a structure of thefirst semiconductor pattern SP1.

A first insulation layer 10 may be disposed on the first semiconductorpattern SP1. The first insulation layer 10 may include at least one ofan inorganic material and/or an organic material. For example, the firstinsulation layer 10 may include a silicon nitride and/or a siliconoxide.

The first insulation layer 10 may be disposed on the buffer layer BFL,and may cover at least a portion of the first semiconductor pattern SP1.Meanwhile, this structure may be illustrated by way of another example.For example, the first insulation layer 10 may be an insulation patternoverlapping the second area AR12 when viewed in a plane in the thirddirection DR3. The first insulation layer 10, according to an exemplaryembodiment of the present inventive concept, may have various shapes,and may not be limited to any one exemplary embodiment.

The first control electrode CE1 and the first capacitor electrode CPE1may be disposed on the first insulation layer 10. The first controlelectrode CE1 and the first capacitor electrode CPE1 may be disposed onsubstantially the same layer.

The first control electrode CE1 may overlap at least the second areaAR12. The first control electrode CE1 may be spaced apart from the firstsemiconductor pattern SP1 by the first insulation layer 10 in-between.

The first capacitor electrode CPE1 may define one electrode of thecapacitor CST. In this exemplary embodiment, the first capacitorelectrode CPE1 may be electrically connected to the first controlelectrode CE1. In another exemplary embodiment, the first capacitorelectrode CPE1 and the first control electrode CE1 may be a conductivepattern having an integral shape.

As shown in FIG. 2, a protection layer PTL may be disposed on the firstcontrol electrode CE1 and the first capacitor electrode CPE1. Theprotection layer PTL may be disposed on the first insulation layer 10,and may cover the first control electrode CE1 and the first capacitorelectrode CPE1. A portion of the protection layer PTL may be in contactwith the first insulation layer 10. A portion of the first insulationlayer 10 that does not overlap the first control electrode CE1 and thefirst capacitor electrode CPE1 may be covered by the protection layerPTL.

The protection layer PTL may include at least one of an inorganicmaterial and/or an organic material. The protection layer PTL mayinclude a different material than the first insulation layer 10. Forexample, the protection layer PTL may include a metal oxide such as analuminum oxide. The protection layer PTL may protect the firstinsulation layer 10 in a subsequent process, where a detailedexplanation thereof will be described.

A second semiconductor pattern SP2 may be disposed on the protectionlayer PTL. The second semiconductor pattern SP2 may include an oxidesemiconductor. For example, the oxide semiconductor may include an oxideof metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn),titanium (Ti), or the like, or an oxide of metal mixture such as zinc(Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti), or the like.

Meanwhile, the second semiconductor pattern SP2 may include acrystallized oxide semiconductor. Grains of the crystallized oxidesemiconductor may have a directionality which is vertical with respectto the surface of the oxide semiconductor.

The second semiconductor pattern SP2 may be divided into a first areaAR21 and a third area AR23 with both the first and third areas AR11,AR13 including impurities, and a second area AR22 which may be adjacentto the first area AR21 and the third area AR23. The first area AR21, andthe third area AR23 may be spaced apart from each other by the secondarea AR22 in-between. The second area AR22 may be a channel region ofthe second transistor T2.

The second area AR22 may be a passage in which an electron moves or ahole moves depending on a structure of the second semiconductor patternSP2.

Regarding the second semiconductor pattern SP2, the impurities mayinclude a reduced metal element. For example, the first area AR21 andthe third area AR23 may include the metal element reduced from metaloxides forming the second area AR22. Accordingly, the second transistorT2 may have reduced leakage current, and may serve as a switchingelement with improved on/off properties.

A second insulation layer including a plurality of insulation patterns21 to 23 may be disposed on the protection layer PTL. The plurality ofinsulation patterns 21 to 23 may include a first insulation pattern 21,a second insulation pattern 22, and a third insulation pattern 23.

The first insulation pattern 21 may be disposed on the secondsemiconductor pattern SP2. The first insulation pattern 21 may overlapat least the second area AR22 of the second semiconductor pattern SP2.For example, the first insulation pattern 21 may cover the second areaAR22 of the second semiconductor pattern SP2, and may not cover thefirst area AR21 and the third area AR23 to expose the first area AR21and the third area AR23.

The second insulation pattern 22 and the third insulation pattern 23 maybe respectively disposed on the protection layer PTL. The secondinsulation pattern 22 and the third insulation pattern 23 mayrespectively come into contact with the protection layer PTL. Meanwhile,in this exemplary embodiment, the second insulation pattern 22 and thethird insulation pattern 23 may be a single pattern connected to eachother.

On the first to third insulation patterns 21 to 23, the second controlelectrode CE2, an upper electrode CE-U, and the second capacitorelectrode CPE2 may be disposed. The second control electrode CE2 may bedisposed on the first insulation pattern 21. In one example, the secondcontrol electrode CE2 may overlap at least the first insulation pattern21. For example, an edge of the first insulation pattern 21 may bearranged along a corresponding edge of the second control electrode CE2.The second control electrode CE2 may have substantially the same shapeas the first insulation pattern 21 on a plane when viewed in the DR3direction.

The second capacitor electrode CPE2 may be disposed on the thirdinsulation pattern 23 of the capacitor CST. The second capacitorelectrode CPE2 may overlap at least the third insulation pattern 23. Thesecond capacitor electrode CPE2 may come in contact with the thirdinsulation pattern 23.

The second capacitor electrode CPE2 may define another electrode of thecapacitor CST. Between the first capacitor electrode CPE1 and the secondcapacitor electrode CPE2, the protection layer PTL and the thirdinsulation pattern 23 may be disposed. The capacitor, according to anexemplary embodiment of the present inventive concept, may define anelectric field in the third insulation pattern 23 and the protectionlayer PTL by means of a potential difference applied between the firstcapacitor electrode CPE1 and the second capacitor electrode CPE2.

The upper electrode CE-U may be disposed on the second insulationpattern 22. The upper electrode CE-U may be disposed on substantiallythe same layer as the second capacitor electrode CPE2. For example, boththe upper electrode CE-U and the second capacitor electrode CPE2 may berespectively formed on the second insulation pattern 22 and the thirdinsulation pattern 23. As shown in FIG. 2, the upper electrode CE-U mayoverlap at least the second insulation pattern 22. An edge of the secondinsulation pattern 22 may be arranged along a corresponding edge of theupper electrode CE-U. The upper electrode CE-U may have substantiallythe same shape as the second insulation pattern 22 on a plane whenviewed in the DR3 direction.

The upper electrode CE-U may receive a different electric signal thanthe first control electrode CE1. The upper electrode CE-U, according toan exemplary embodiment of the present inventive concept, may beelectrically connected to the second capacitor electrode CPE2. Inanother exemplary embodiment, the upper electrode CE-U and the secondcapacitor electrode CPE2 may be a conductive pattern having an integralshape.

A third insulation layer 30 may be disposed on the second controlelectrode CE2, the upper electrode CE-U, and the second capacitorelectrode CPE2. The third insulation layer 30 may be disposed on theprotection layer PTL and may cover the second control electrode CE2, theupper electrode CE-U, and the second capacitor electrode CPE2, as shownin FIG. 2. The third insulation layer 30 may cover an upper surface anda side surface of the second control electrode CE2, an upper surface anda side surface of the second capacitor electrode CPE2, an upper surfaceand a side surface of the upper electrode CE-U, and each side surface ofthe first to third insulation patterns 21 to 23. The third insulationlayer 30 may include an organic material and/or an inorganic material.

The third insulation layer 30 may be thicker than the protection layerPTL. In one example, as shown in FIG. 2, the third insulation layer 30may be formed to provide a flat surface above the second controlelectrode CE2, the upper electrode CE-U, and the second capacitorelectrode CPE2. Accordingly, one or more elements disposed above thesecond control electrode CE2, the upper electrode CE-U, and the secondcapacitor electrode CPE2 may be disposed on the flat surface of thethird insulation layer 30.

On the third insulation layer 30, the first input electrode IE1, thefirst output electrode OE1, the second input electrode IE2, and thesecond output electrode OE2 may be disposed. The first input electrodeIE1, the first output electrode OE1, the second input electrode IE2, andthe second output electrode OE2 may respectively overlap the first areaAR11 and the third area AR13 of the first semiconductor pattern SP1, andthe first area AR21 and the third area AR23 of the second semiconductorpattern SP2 on a plane when viewed in the DR3 direction. The first inputelectrode IE1, the first output electrode OE1, the second inputelectrode IE2, and the second output electrode OE2 may penetrate to beconnected to the first semiconductor pattern SP1 or the secondsemiconductor pattern SP2. For example, the first input electrode IE1and the first output electrode OE1 may respectively penetrate at least aportion of the first insulation layer 10, the protection layer PTL, andthe third insulation layer 30 to be connected to the first semiconductorpattern SP1, and the second input electrode IE2 and the second outputelectrode OE2 may respectively penetrate at least the third insulationlayer 30 to be connected to the second semiconductor pattern SP2.

In this example, the first input electrode IE1 and the first outputelectrode OE1 may be respectively connected to the first area AR11, andthe third area AR13 of the first semiconductor pattern SP1 through firstpenetration portions OP1, where the first penetration portions OP1 maypenetrate the first insulation layer 10, the protection layer PTL, andthe third insulation layer 30. The second input electrode IE2 and thesecond output electrode OE2 may be respectively connected to the firstarea AR21, and the third area AR23 of the second semiconductor patternSP2 through second penetration portions OP2, which may penetrate thethird insulation layer 30.

An intermediate film ILD may be disposed on the third insulation layer30. The intermediate film ILD may include an inorganic material and/oran organic material. On the intermediate film ILD, a third penetrationportion OP3 penetrating the intermediate film ILD may be defined. Thethird penetration portion OP3 may be defined in a portion overlappingthe first output electrode OE1, as shown in FIG. 2.

The first electrode ED1 may be disposed on the intermediate film ILD.The first electrode ED1 may be connected to the first output electrodeOE1 of the first transistor T1 through the third penetration portionOP3. The first electrode ED1 may include a conductive material. Thefirst electrode ED1 may be a reflective, or a transmissive electrode,but not limited thereto.

A pixel definition film PLD may be disposed on the intermediate filmILD. The pixel definition film PLD may include an organic film and/or aninorganic film. On the pixel definition film PLD, a predeterminedopening portion OP-PX may be defined. The opening portion OP-PX mayexpose at least a portion of the first electrode ED1.

On the first electrode ED1, the first charge control layer HCL, thelight emitting layer EML, the second charge control layer ECL, and thesecond electrode ED2 may be sequentially laminated. The first electrodeED1, the first charge control layer HCL, the light emitting layer EML,the second charge control layer ECL, and the second electrode ED2 mayconstitute the organic light emitting diode OLED.

The first charge control layer HCL may include a holeinjection/transport material, and the second charge control layer ECLmay include an electron injection/transport material. Alternately, thefirst charge control layer HCL may include an electroninjection/transport material, and the second charge control layer ECLmay include a hole injection/transport material. The first chargecontrol layer HCL and the second charge control layer ECL mayrespectively include one or more layers.

The light emitting layer EML may include a light emitting material. Thelight emitting layer EML may be a light emitting pattern overlapping theopening portion OP-PX. The light emitting layer EML may include one ormore layers. Meanwhile, although not shown, a plurality of the lightemitting layer EML may be provided and disposed to form a multilayeredstructure.

The second electrode ED2 may be disposed on the second charge controllayer ECL. The second electrode ED2 may overlap at least the firstelectrode ED1. In this exemplary embodiment, the second electrode ED2may overlap substantially the pixel definition layer PDL entirely.

The second electrode ED2 may include a conductive material. The secondelectrode may be a transmissive electrode or a reflective electrode. Theorganic light emitting diode OLED may generate light from the lightemitting layer EML using a voltage difference applied between the firstelectrode ED1 and the second electrode ED2.

In another exemplary embodiment, although not shown, the organic lightemitting diode OLED may further includes at least one charge generationlayer disposed between the first electrode ED1 and the second electrodeED2.

In another exemplary embodiment, although not shown, the semiconductordevice SD1 may further include an organic film and/or an inorganic filmdisposed on the second electrode ED2.

The semiconductor device SD1, according to an exemplary embodiment ofthe present inventive concept, may protect the first insulation layer 10from subsequent process by further including the protection layer PTL.Accordingly, the first insulation layer 10 may be stably maintainedduring the subsequent process, and a short circuit or a leakage currentdue to the damage of the first insulation layer 10 may be prevented. Adetailed explanation thereof will be described later.

FIG. 3 is a cross-sectional view showing a portion of a semiconductordevice according to an exemplary embodiment of the present inventiveconcept. In FIG. 3, a semiconductor device SD2 will be described.Meanwhile, it is noted that the same elements as the elements describedin FIG. 1 and FIG. 2 may be assigned the same reference numerals, andduplicate descriptions will be omitted.

As shown in FIG. 3, the semiconductor device SD2 may include the firsttransistor T1, the second transistor T2, the capacitor CST, and theorganic light emitting diode OLED. In this example, the semiconductordevice SD2 may omit the second insulation pattern 22 and an upperelectrode CE-U, which were previously shown in FIG. 2. Accordingly, anAA region above the first control electrode CE1 may not include aninsulation layer, and the semiconductor device SD2 may include the firstinsulation pattern 21, and the third insulation pattern 23, as shown inFIG. 3.

As shown in FIG. 3, the semiconductor device SD2, according to anexemplary embodiment of the present inventive concept, does not includea separate conductive pattern overlapping the first control CE1, and thefirst transistor T1 may be operated with ease by having a single firstcontrol electrode CE1.

FIG. 4A is a cross-sectional view showing a portion of a semiconductordevice according to an exemplary embodiment of the present inventiveconcept. FIG. 4B is a cross-sectional view showing a portion of asemiconductor device according to an exemplary embodiment of the presentinventive concept. Semiconductor devices SD3 and SD4 will be describedin view of FIG. 4A and FIG. 4B. Meanwhile, it is noted that the elementsin FIGS. 4A and 4B, which are same as the elements described in FIG. 2to FIG. 3 may be assigned the same reference numerals, and duplicatedescriptions will be omitted.

As shown in FIG. 4A and FIG. 4B, the semiconductor devices SD3 and SD4may respectively include the first transistor T1 and the secondtransistor T2. The first transistor T1 and the second transistor T2 mayrespectively correspond to the first transistor T1 and the secondtransistor T2 illustrated in FIG. 2.

A capacitor may be defined on the first semiconductor pattern SP1. Thecapacitor may be defined by the first control electrode CE1 and theupper electrode CE-U. Accordingly, the first control electrode CE1 maybecome an element of the first transistor T1 and the capacitor at thesame time.

Meanwhile, the capacitor may have various capacitances according to adielectric layer disposed between the first control electrode CE1 andthe upper electrode CE-U. In another example, capacitances may also varydepending on a location in which the upper electrode CE-U is disposed.

For example, as shown in FIG. 4A, the upper electrode CE-U may bedisposed on the second insulation pattern 22 and the protection layerPTL. Accordingly, a capacitance of a capacitor, which is defined by thefirst control electrode CE1 and the upper electrode CE-U, may beinfluenced by both the second insulation pattern 22 and the protectionlayer PTL. For example, the capacitor may be influenced by the thicknessand a material of the second insulation pattern 22 and the protectionlayer PTL, respectively. In this exemplary embodiment, the secondinsulation pattern 22 may correspond to the second insulation layer 22as illustrated in FIG. 2.

Also, for example, as shown in FIG. 4B, the upper electrode CE-U may bedisposed on the first control electrode CE1 with only the protectionlayer PTL in-between. In this exemplary embodiment, the semiconductordevice SD4 may include a second insulation layer 20-1 having a differentshape than that of the semiconductor device SD3 of FIG. 4A. For example,the second insulation layer 20-1 of FIG. 4B may have a different shapethan the second insulation layer 21 of FIG. 4A.

In this exemplary embodiment, the second insulation layer 20-1 may bedisposed between the second semiconductor pattern SP2 and the secondcontrol electrode CE2. The second insulation layer 20-1 may be a singleinsulation pattern overlapping the second area AR22 of the secondsemiconductor pattern SP2. When viewed in the direction of DR3, thesecond insulation layer 20-1, on a plane, may not cover the first areaAR11 and the third area AR13, to expose the first area AR11 and thethird area AR13 of the second semiconductor pattern SP2, and may cover asecond area AR12. The boundary between the first area AR21 and thesecond area AR22, and the boundary between the second area AR22 and thethird area AR23 may be arranged along a side surface of the secondinsulation layer 20-1.

Meanwhile, in this exemplary embodiment, the upper electrode CE-U may bedisposed on the first control electrode CE1, and may form an electricfield with the first control electrode CE1. Accordingly, the upperelectrode CE-U may become one electrode constituting the capacitor, andthe first control electrode CE1 may become the other electrodeconstituting the capacitor.

In this exemplary embodiment, the upper electrode CE-U may directly bedisposed on the protection layer PTL. The protection layer PTL may bedisposed between the upper electrode layer CE-U and the first controlelectrode CE1 and may serve as a dielectric layer of a capacitor definedby the upper electrode CE-U and the first control electrode CE1.Accordingly, the capacitor defined by the upper electrode CE-U and thefirst control electrode CE1 may be influenced by the thickness of theprotection layer PTL and a material constituting the protection layerPTL.

The semiconductor device SD4 according to an exemplary embodiment of thepresent inventive concept may include a capacitor using the singleprotection layer PTL as a dielectric layer such that the capacitance ofthe capacitor may be controlled by controlling physical properties, suchas the thickness or material, of the protection layer PTL only.

FIGS. 5A through 5M are cross-sectional views showing a method ofmanufacturing a semiconductor device according to exemplary embodimentsof the present inventive concept. FIGS. 5A through 5M illustrate amethod of manufacturing the semiconductor device SD1 in FIG. 2 by way ofan example, which will be described hereafter.

As shown in FIG. 5A, the buffer layer BFL and a pre first semiconductorpattern SP1-A may be provided on the base substrate SUB. The bufferlayer BFL may be provided by depositing, coating, or printing aninorganic material and/or an organic material on the base substrate SUB.Meanwhile, the semiconductor device SD1, according to an exemplaryembodiment of the present inventive concept, may operate without thebuffer layer BFL.

In one example, the pre first semiconductor pattern SP1-A may beprovided on the base substrate SUB or the buffer layer BFL. The prefirst semiconductor pattern SP1-A may be provided by depositing acrystalline semiconductor material followed by patterning the depositedcrystalline semiconductor material.

Hereafter, as shown in FIG. 5B, a pre first insulation layer 10-A and aconductive layer CL may be provided. The pre first insulation layer 10-Amay be provided by depositing, coating, or printing an inorganicmaterial and/or an organic material on the base substrate SUB or thebuffer layer BFL. The pre first insulation layer 10-A may cover the prefirst semiconductor pattern SP1-A. In one example, the conductive layerCL may be formed by depositing a conductive material on the pre firstinsulation layer 10-A.

After a first conductive pattern may be formed from the conductive layerCL, as shown in FIG. 5C, the first semiconductor pattern SP1 may beformed. The first conductive pattern may be formed on the pre firstinsulation layer 10-A. The first conductive pattern may include thefirst control electrode CE1 and the first capacitor electrode CPE1.

For example, the first control electrode CE1 and the first capacitorelectrode CPE1 may be formed by patterning the conductive layer CL. Thefirst control electrode CE1 and the first capacitor electrode CPE1 maybe simultaneously patterned using the same mask. Meanwhile, in anotherexample, the first control electrode CE1 and the first capacitorelectrode CPE1 may respectively be patterned using different masks.

The first semiconductor pattern SP1 may be formed by implantingimpurities DM to the pre first semiconductor pattern SP1-A. Theimpurities DM, for example, may be implanted into the pre firstsemiconductor pattern SP1-A by a diffusion process, or an ion implantingprocess, but not limited to a specific method.

The impurities DM may include various materials. For example, theimpurities DM may include a trivalent element. In this example, thefirst semiconductor pattern SP1 may be provided as a p-typesemiconductor. In another example, the impurities DM may include apentavalent element. In this example, the first semiconductor patternSP1 may be provided as an n-type semiconductor.

The impurities DM may be implanted into a portion of the pre firstsemiconductor pattern SP1-A. For example, the impurities DM may beplanted into a portion that does not overlap the first control electrodeCE1, and the pre first semiconductor pattern SP1-A (as shown in FIG. 5B)may be changed to the first semiconductor pattern SP1 which is dividedinto the first area AR11, the second area AR12, and the third area AR13.In this example, the first area AR11 and the third area AR13 may beprovided with the impurities DM by a diffusion process, or an ionimplantation process etc. Accordingly, the impurities DM may be includedin the first area AR11 and the third area AR13 of the firstsemiconductor pattern SP1.

As shown in FIG. 5D, an pre protection layer PTL-A and an pre secondsemiconductor pattern SP2-A may be formed. The pre protection layerPTL-A may be formed by depositing, coating, or printing an organicmaterial and/or an inorganic material on the pre first insulation layer10-A. The pre protection layer PTL-A may be provided to substantiallyentirely cover the first control electrode CE1 and the first capacitorelectrode CPE1.

An pre second semiconductor pattern SP2-A is formed. The pre secondsemiconductor pattern SP2-A may be formed by forming a material layerincluding an oxide semiconductor on the pre protection layer PTL-A andthen by patterning the firmed oxide semiconductor. The oxidesemiconductor, as described above, may include an oxide of metal such aszinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti), or thelike, or an oxide of metal mixture such as zinc (Zn), indium (In),gallium (Ga), tin (Sn), titanium (Ti), or the like.

As shown in FIG. 5E, an pre second insulation layer 20-A, the secondcontrol electrode CE2, the upper electrode CE-U, and the secondcapacitor electrode CPE2 may be formed on the pre protection layerPTL-A. The pre second insulation layer 20-A may be formed by deposition,coating, or printing an organic material and/or an inorganic material onthe pre protection layer PTL-A.

A second conductive pattern including the second control electrode CE2and the second capacitor electrode CPE2 may be formed on the pre secondinsulation layer 20-A. The second control electrode CE2 and the secondcapacitor electrode CPE2 may be formed by depositing a conductivematerial on the pre second insulation layer 20-A and then by patterningthe deposited conductive material. The second control electrode CE2 andthe second capacitor electrode CPE2 may be simultaneously patternedusing one mask. Accordingly, processing cost may be reduced andprocessing time may be shortened.

Meanwhile, the second conductive pattern may further include an upperelectrode CE-U. The upper electrode CE-U may be formed to overlap thefirst control electrode CE1 on a plane when viewed in the DR3 direction.For example, the upper electrode CE-U may be simultaneously patternedwith the second control electrode CE2 and the second capacitor electrodeCPE2 using one mask. In this example, the upper electrode CE-U may beformed to be connected to the second capacitor electrode CPE2 to have anintegral shape.

As shown in FIG. 5F, the first insulation pattern 21, the secondinsulation pattern 22, and the third insulation pattern 23 may beformed. The first insulation pattern 21, the second insulation pattern22, and the third insulation pattern 23 may be formed by patterning thepre second insulation layer 20-A using, for example, an etching gas ET.

In this example, the first insulation pattern 21, the second insulationpattern 22, and the third insulation pattern 23 may be respectivelypatterned using the first control electrode CE1, the upper electrodeCE-U, and the second capacitor electrode CPE2 as masks. End portions ofthe first insulation pattern 21, the second insulation pattern 22, andthe third insulation pattern 23 may be respectively arranged along endportions of the first control electrode CE1, the upper electrode CE-U,and the second capacitor electrode CPE2.

Meanwhile, the etch rate for the pre protection layer PTL-A may be lowerthan that of the pre second insulation layer 20-A with respect to theetching gas ET. For example, the pre protection layer PTL-A may includea material such that a etch selectivity for the pre second insulationlayer 20-A may be higher than that of the pre protection layer PTL-Awith respect to the etching gas ET. Herein a high etch selectivity maybe equivalent to a high etch rate, and a low etch selectivity may beequivalent to a low etch rate. For example, in the case that the presecond insulation layer 20-A includes a silicon oxide, the preprotection layer PTL-A may include an aluminum oxide, where the etchrate for the silicon oxide may be greater than the etch rate for thealuminum oxide.

For example, the etching rate of the pre protection layer PTL-A withrespect to the etching gas ET may be less than the etching rate of thepre second insulation layer 20-A with respect to the etching gas ET.Therefore, the pre protection layer PTL-A may not be etched while thepre second insulation layer 20-A is being etched by the etching gas ET.Even in the case that the pre second insulation layer 20-A has beenexcessively etched during the extended etching processing time, the prefirst insulation layer 10-A disposed under the pre protection layerPTL-A may be protected by the pre protection layer PTL-A without beingaffected by the etching gas ET.

For example, in a method of manufacturing a semiconductor deviceaccording to an exemplary embodiment of the present inventive concept,even if the first insulation layer 10-A disposed under the preprotection layer PTL-A includes substantially the same material as thepre second insulation layer 20-A, or includes a material having higheretch rate than the pre second insulation layer 20-A with respect to theetching gas ET, the initial insulation layer 10-A may be protected bythe pre protection layer PTL-A during the subsequent process in whichthe first insulation pattern 21, the second insulation pattern 22, andthe third insulation pattern 23 may be formed. Accordingly, the firstinsulation layer 10-A may be formed of various materials having nolimitation in constituting materials. For example, the first insulationlayer 10-A may be formed of either a material with a substantially highetch rate or a material with a substantially low etch rate, with respectto the etching gas ET.

FIG. 5G illustrates that an initial third insulation layer 30-A may beformed. The initial third insulation layer 30-A may be formed bydeposition, coating, or printing an inorganic material and/or an organicmaterial on the pre protection layer PTL-A. The initial third insulationlayer 30-A may cover the second control electrode CE2, the upperelectrode CE-U, and the second capacitor electrode CPE2, and may beformed to be thick enough to have a flat surface provided on an upperside thereof.

Meanwhile, at least a portion of the second semiconductor pattern SP2-Amay include selectively reduced metal element. For example, at least aportion of the pre second semiconductor pattern SP2-A may be blocked bythe first insulation pattern 21 to form the second area AR22, and atleast a portion of the pre second semiconductor pattern SP2-A may beexposed from the first insulation pattern 21, to form the first areaAR21 and the third area AR23. The second semiconductor pattern SP2 maybe divided into the first area AR21, the second area AR22, and the thirdarea AR23. The exposed first area AR21 and third area AR23 may include ametal element reduced from a metal oxide while the second area AR22 mayinclude the metal oxide.

FIG. 5H illustrates that first penetration portions OP1 and secondpenetration portions OP2 may be formed to form the first insulationlayer 10, the protection layer PTL, and the third insulation layer 30.For example, the first penetration portions OP1 may be provided byrespectively penetrating the pre first insulation layer 10-A, the preprotection layer PTL-A, and the initial third insulation layer 30-A. Thefirst penetration portions OP1 may be respectively defined in the firstarea AR11 and the third area AR13 of the first semiconductor pattern SP1and expose at least a portion of the first area AR11, and at least aportion of the third area AR13.

The second penetration portions OP2 may be provided by respectivelypenetrating the initial third insulation layer 30-A. The secondpenetration portions OP2 may be respectively defined in the first areaAR21 and the third area AR23 of the second semiconductor pattern SP2 andexpose at least a portion of the first area AR21 and at least a portionof the third area AR23.

Hereafter, as shown in FIG. 5I, the first input electrode IE1, the firstoutput electrode OE1, the second input electrode IE2, and the secondoutput electrode OE2 may be formed. The first input electrode IE1, thefirst output electrode OE1, the second input electrode IE2, and thesecond output electrode OE2 may be formed by forming a layer including aconductive material on the third insulation layer 30 and then bypatterning the layer.

For example, the first input electrode IE1, the first output electrodeOE1, the second input electrode IE2, and the second output electrode OE2may fill the first penetration portions OP1 and the second penetrationportions OP2, respectively. The first input electrode IE1 and the firstoutput electrode OE1 may be respectively connected to the first areaAR11 of the first semiconductor pattern SP1 and the third area AR13 ofthe first semiconductor pattern SP1 through the first penetrationportions OP1, and may constitute the first transistor T1. The secondinput electrode IE2 and the second output electrode OE2 may berespectively connected to the first area AR21 of the secondsemiconductor pattern SP2 and the third area AR23 of the secondsemiconductor pattern SP2, and may constitute the second transistor T2.

Hereafter, as shown in FIG. 5J, an initial intermediate film ILD-A maybe formed on the third insulation layer 30. The initial intermediatefilm ILD-A may be formed by deposition, coating, or printing aninorganic material and/or an organic material on the third insulationlayer 30.

Hereafter, as shown in FIG. 5K, an intermediate film ILD and a lowerelectrode ED1 may be formed. The intermediate film ILD may be formed bydefining a third penetration portion OP3 configured to penetrate theinitial intermediate film ILD-A. In one example, the third penetrationportion OP3 may be provided until the third penetration portion OP3reaches the first output electrode OE1 to overlap the first outputelectrode OE1.

The lower electrode ED1 may be formed by forming a conductive materialon the intermediate film ILD and then by patterning the formedconductive material. The lower electrode ED1 may be connected to thefirst output electrode OE1 through the third penetration portion OP3.

Hereafter, as shown in FIG. 5L, a pixel definition film PDL may beformed on the intermediate film ILD. The pixel definition film PDL maybe formed by deposition, coating, or printing an organic material and/oran inorganic material on the intermediate film ILD, and then by defininga predetermined opening portion OP-PX. The opening portion OP-PX mayexpose at least a portion of the lower electrode ED1.

FIG. 5M illustrates forming an organic light emitting diode OLED. Asshown in FIG. 5M, a first charge control layer HCL, a light emittinglayer EML, a second charge control layer ECL, and a second electrode ED2may be sequentially formed on the pixel definition film PDL. The firstelectrode ED1, the first charge control layer HCL, the light emittinglayer EML, the second charge control layer ECL, and the second electrodeED2 may constitute the organic light emitting diode OLED. Meanwhile, thefirst charge control layer HCL, the light emitting layer EML, and thesecond charge control layer ECL may be respectively formed by a singleprocess, or by multiple processes.

As described above, according to an exemplary embodiment of the presentinventive concept, stability of the first insulation layer 10 may beimproved due to the protection layer PTL or the pre protection layerPTL-A that is formed on the first insulation layer 10. Accordingly, asemiconductor device with improved reliability may be provided.

FIGS. 6A through 6G are cross-sectional views showing a method ofmanufacturing a semiconductor device according to an exemplaryembodiment of the present inventive concept. In FIGS. 6A through 6G, thesemiconductor device SD3 (as shown in FIG. 4) may be illustrated.Hereafter, referring to FIG. 6A through FIG. 6G, a method ofmanufacturing the semiconductor device SD3 will be described. It isnoted that the same elements in FIG. 6A through FIG. 6G as the elementsdescribed in FIG. 4 may be assigned the same reference numerals.

As shown in FIG. 6A, a buffer layer BFL may be formed on the basesubstrate SUB, and then the first semiconductor pattern SP1, the initialinsulation layer 10-A, the first control electrode CE1, the preprotection layer PTL-A, and the pre second semiconductor pattern SP2-Amay be formed. Detailed explanation of forming the first semiconductorpattern SP1, the initial insulation layer 10-A, the first controlelectrode CE1, the pre protection layer PTL-A, and the pre secondsemiconductor pattern SP2-A may be substantially similar to the formingmethod described for FIG. 5A through FIG. 5D.

Hereafter, as shown in FIG. 6B, a pre second insulation layer 20-A1 maybe formed on the pre protection layer PTL-A. The pre second insulationlayer 20-A1 may be formed by deposition, coating, or printing an organicmaterial and/or an inorganic material on the pre protection layer PTL-A,and then by patterning the formed pre second insulation layer 20-A1. Thepre second insulation layer 20-A1 may be an insulation pattern 20-1covering at least the pre second semiconductor pattern SP2-A.

Hereafter, as shown in FIG. 6C, a second conductive pattern may beformed on the pre protection layer PTL-A. The second conductive patternmay include a pre second control electrode CE2-A, and the upperelectrode CE-U. The pre protection layer PTL-A may cover an uppersurface and a side surface of the pre second insulation layer 20-A1 inFIG. 6C, and may cover a side surface of the pre second semiconductorpattern SP2-A.

The pre second control electrode CE2-A may be formed by depositing,coating, or printing a conductive material on the pre protection layerPTL-A, and then by patterning the formed conductive material.

The upper electrode CE-U may be formed to overlap the first controlelectrode CE1. The upper electrode CE-U and the pre second controlelectrode CE2-A may be simultaneously formed using one mask.

Hereafter, as shown in FIG. 6D and FIG. 6E, the second control electrodeCE2 and the second insulation pattern 20-1 may be formed. The secondcontrol electrode CE2 may be formed by patterning the pre second controlelectrode CE2-A. Meanwhile, this may be illustrated by way of anotherexample. The second control electrode CE2 may be simultaneously formedwith the upper electrode CE-U.

The second insulation layer 20-1 may be formed by patterning the presecond insulation layer 20-A1. The second insulation layer 20-1 may bepatterned using the second control electrode CE2 as a mask. As describedabove, injected etching gas ET may remove a portion of the pre secondinsulation layer 20-A1, which may be exposed and patterned by the secondcontrol electrode CE2 as a mask. Accordingly, the second insulationlayer 20-1 may have a shape of an insulation pattern arranged along anend portion of the second control electrode CE2. For example, the secondinsulation layer 20-1 may have substantially the same shape as thesecond control electrode CE2 when viewed in the direction of DR3.

Meanwhile, while the etching gas ET is etching the pre second insulationlayer 20-A1, the pre protection layer PTL-A may cover the pre firstinsulation layer 10-A. As described above, the pre protection layerPTL-A may be formed of a material having a substantially low etch ratewith respect to the etching gas ET, and the etching gas ET may have alarge etch selectivity for the pre second insulation layer 20-A1.According to a method of manufacturing a semiconductor device accordingto an exemplary embodiment of the present inventive concept, when thesecond insulation layer 20-1 is formed, the pre first insulation layer10-A may be prevented from being damaged by the etching gas ET due tothe presence of the pre protection layer PTL-A.

Hereafter, as shown in FIG. 6F, the initial third insulation layer 30-Ais formed. The initial third insulation layer 30-A may be formed bydepositing, coating, or printing an inorganic material and/or an organicmaterial on the pre protection layer PTL-A. The initial third insulationlayer 30-A may be formed to be thick enough to cover the second controlelectrode CE2 and the upper electrode CE-U, and to have a flat surfaceformed on an upper side of the second control electrode CE2 and theupper electrode CE-U.

Meanwhile, at least a portion of the pre second semiconductor patternSP2-A may be exposed from the second insulation layer 20-1, and reducedto formed the second semiconductor pattern SP2, which may be dividedinto the first area AR21, the second area AR22, and the third area AR23.A detailed explanation thereof is redundant with the description of theFIG. 5G, and therefore will be omitted.

Hereafter, as shown in FIG. 6G, a first insulation layer 10, aprotection layer PTL, and a third insulation layer 30 may be formed byforming first penetration portions OP1 and second penetration portionsOP2, and a first transistor T1 and a second transistor T2 may be formedby forming the first input electrode IE1, the first output electrodeOE1, the second input electrode IE2, and the second output electrode OE2on the third insulation layer 30. A detailed explanation thereofcorresponds to FIG. 5G, and a redundant explanation will be omitted.

According to an exemplary embodiment of the present inventive concept,in the process of forming the second insulation layer 20-1, the firstinsulation layer 10 may be prevented from being damaged by including theprocess of forming the protection layer PTL on the first insulationlayer 10. Therefore, the process reliability of the first insulationlayer 10 may be improved.

According to an exemplary embodiment of the present inventive concept,in a process for manufacturing a semiconductor device includingdifferent semiconductor patterns, an insulation layer may be preventedfrom being damaged in the subsequent process. Accordingly, currentleakage is minimized and short circuits may be prevented.

Also, according an exemplary embodiment of the present inventiveconcept, a semiconductor device including an element with improvedreliability may be provided by protecting an insulation layer in asubsequent process.

The above-disclosed subject matter is to be considered illustrative andnot restrictive, and the appended claims are intended to cover all suchmodifications, enhancements, and other exemplary embodiments, which fallwithin the true spirit and scope of the inventive concept. Thus, to themaximum extent allowed by law, the scope of the inventive concept is tobe determined by the broadest permissible interpretation of thefollowing claims and their equivalents, and shall not be restricted orlimited by the foregoing detailed description.

What is claimed is:
 1. A semiconductor device comprising: a basesubstrate; a first transistor disposed on a first surface of the basesubstrate, the first transistor comprising a first input electrode, afirst output electrode, a first control electrode, and a firstsemiconductor pattern including a crystalline semiconductor; a secondtransistor disposed on the first surface of the base substrate, thesecond transistor comprising a second input electrode, a second outputelectrode, a second control electrode, and a second semiconductorpattern including an oxide semiconductor; a first insulation layer and asecond insulation layer disposed on the first surface of the basesubstrate; a protection layer disposed above the first control electrodeand under the second insulation layer, wherein the protection layerincludes a metal oxide, a first capacitor electrode disposed above thefirst insulation layer and under the protection layer and secondinsulation layer, and a second capacitor electrode disposed above theprotection layer and second insulation layer and that defines anelectric field with the first capacitor electrode wherein the secondsemiconductor pattern is disposed above the protection layer, the secondcontrol electrode is disposed above the second semiconductor pattern,and wherein the first semiconductor pattern and the second semiconductorpattern are disposed on different layers with the protection layertherebetween.
 2. The semiconductor device of claim 1, wherein the firstinsulation layer is disposed between the first semiconductor pattern andthe first control electrode, and the protection layer is disposed onabove the first insulation layer.
 3. The semiconductor device of claim1, wherein the second insulation layer is disposed between the secondsemiconductor pattern and the second control electrode, and theprotection layer comprises a material having a first etch selectivitythat is different from a second etch selectivity of the secondinsulation layer.